SUWON, South Korea — The semiconductor industry has spent the past several years solving one of AI computing’s most visible bottlenecks: memory bandwidth.
HBM moved high-bandwidth memory physically closer to the processor. Now another bottleneck is moving into focus — how to move enormous amounts of data out of the processor package and between thousands of AI accelerators without consuming an unsustainable amount of power.
That is the problem Co-Packaged Optics, or CPO, is designed to address.
At ASPS 2026 in Suwon, Samsung presented a CPO architecture showing an optical engine integrated into the same advanced package as logic and HBM. The display provides a useful view of how AI packaging could evolve from a processor-and-memory structure into a tightly integrated computing, memory and optical communications system.
ASPS 2026, held at the Suwon Convention Center from August 26 to 28, brought together 183 companies and approximately 400 booths focused on next-generation semiconductor packaging technologies.
What Changes With CPO?
In a conventional server or network switch, high-speed electrical signals leave the processor or switch ASIC and travel across the printed circuit board before reaching a pluggable optical transceiver mounted near the front panel.
Only there is the electrical signal converted into light and transmitted through optical fiber.
CPO dramatically shortens that electrical path.
Instead of placing the optical conversion module at the edge of the system, the optical engine is placed next to the compute or switching silicon, often on the same substrate or interposer.
The electrical signal may therefore travel only millimeters before entering the optical interface.
HBM brings memory closer to the processor. CPO brings optical communication closer to the processor.
Samsung describes CPO as an architecture capable of integrating optical interfaces directly with switch ASICs and, in its CPO XPU concept, integrating a 3D optical engine with an XPU or GPU on an interposer for AI and high-performance computing applications.
Inside Samsung’s CPO Architecture
The Samsung CPO concept shown in Suwon separates the optical engine into several important functional blocks.
The optical path begins with the optical fiber, which connects through a Fiber Array Unit, or FAU. The FAU precisely positions multiple fibers so that light can enter or leave the optical package.
A receptacle provides the mechanical optical interface, while an Optical Block guides the light between the fiber assembly and the photonic chip.
At the semiconductor level, two components become particularly important:
- PIC — Photonic Integrated Circuit: performs optical-electrical and electrical-optical signal conversion.
- EIC — Electronic or Electrical Integrated Circuit: amplifies, drives and controls the high-speed electrical signals connected to the photonic device.
These optical components sit alongside the main compute package containing Logic and HBM, with an interposer and substrate forming the high-density connection platform underneath.
A heat spreader sits above the primary compute elements to manage the increasingly concentrated thermal load.
Why Copper Is Becoming the Problem
Copper interconnect has supported the computing industry for decades, but its job becomes much harder as signaling rates rise.
At higher SerDes speeds, electrical channels become increasingly sensitive to insertion loss, crosstalk, reflections and other signal-integrity effects. Driving a signal farther across a PCB requires increasingly sophisticated equalization and, in some architectures, retimers or additional signal-conditioning circuitry.
Those solutions can extend electrical reach, but they also consume power.
Optical fiber operates under fundamentally different constraints. Once information has been converted into light, it can travel much farther with comparatively low transmission loss.
The engineering logic behind CPO is therefore relatively simple:
keep the electrical distance extremely short and use optics for the longer-distance connection.
AI Has Made Interconnect Power a First-Class Problem
The attraction of CPO is not bandwidth alone.
It is increasingly about energy per bit.
Modern AI systems are being built from thousands or tens of thousands of accelerators. Every accelerator requires high-speed communication with other processors, switches and memory systems.
As cluster size expands, the power consumed just moving data becomes significant enough to compete directly with the power available for computation.
This changes the economics of AI infrastructure.
A watt saved in networking can potentially become a watt available to the GPU.
Broadcom provides one indication of the potential scale of the improvement. Its 51.2-Tbps Bailly CPO Ethernet switch integrates eight 6.4-Tbps silicon-photonics optical engines with a Tomahawk 5 switch chip. Broadcom reports more than a 70% reduction in optical-interconnect power consumption compared with standard pluggable-optics implementations for that platform.
That figure should not be interpreted as a universal CPO efficiency number, but it demonstrates why hyperscale AI operators are taking the architecture seriously.
Bandwidth Density Becomes Equally Important
There is another physical constraint: space.
A traditional network switch has a limited front-panel area. The number of pluggable optical modules that can be installed is constrained by the physical dimensions of cages, connectors, cooling requirements and PCB routing.
CPO changes the scaling model.
By moving optical engines directly beside the ASIC, significantly more bandwidth can potentially be concentrated around the package while reducing the high-speed electrical distance between the switch silicon and optical interface.
Broadcom’s Bailly system already demonstrates a 51.2-Tbps CPO switch architecture, while Intel has demonstrated a fully integrated Optical Compute Interconnect chiplet delivering up to 4 Tbps bidirectionally and designed for co-packaging with CPUs, GPUs and other system-on-chip devices.
Intel’s roadmap points toward optical I/O devices capable of reaching tens of terabits per second per device.
Why AI Training Changes the Network Architecture
Traditional computing could often treat networking as infrastructure surrounding the processor.
Large-scale AI changes that relationship.
Distributed training requires accelerators to exchange enormous quantities of intermediate data repeatedly during each training cycle. Operations such as collective communication mean the network can sit directly on the critical path of AI performance.
The result is that the performance of an AI system is increasingly determined not only by how quickly an accelerator calculates, but also by how efficiently thousands of accelerators communicate.
This is why optical I/O is beginning to move closer to the compute silicon itself.
CPO Is Really an Advanced Packaging Problem
Silicon photonics is not a newly discovered technology. The industry has already produced silicon-photonics devices at substantial scale.
The difficult part of CPO is integrating those devices reliably beside very large, expensive and power-hungry AI chips.
This is why Samsung’s CPO presentation emphasizes 3DIC, TCB, HCB and 2.xD packaging.
Samsung identifies Thermo-Compression Bonding (TCB) and Hybrid Copper Bonding (HCB) as important technologies for integrating optical engines and other dies at increasingly fine interconnect pitches.
The company’s 2.xD packaging platform provides the horizontal heterogeneous-integration environment in which logic, HBM and optical components can share a common system-level package.
Samsung’s broader advanced-packaging roadmap includes 2.5D silicon-interposer architectures as well as 3D structures using TCB and next-generation hybrid copper bonding.
Fiber Alignment May Be as Important as Transistors
Optical packaging also introduces manufacturing problems that do not exist in a purely electrical package.
Light must be coupled efficiently between optical fiber, the Optical Block and the PIC. The mechanical relationship among these components must remain highly precise throughout assembly and operation.
The complete package must then survive semiconductor manufacturing processes, temperature cycling and years of operation while remaining aligned closely enough to maintain acceptable optical loss.
That makes assembly accuracy, bonding, fiber attachment, thermal expansion and production yield critical economic factors.
In CPO, having a good photonic device is not enough.
The manufacturer must also be able to package it repeatedly, reliably and at high yield.
Thermal Management Becomes More Complicated
The same integration that improves electrical performance creates a thermal problem.
Logic dies used for AI can dissipate enormous amounts of heat. HBM is positioned immediately beside them, and CPO introduces sensitive photonic and electrical components into the same thermal environment.
Different CPO architectures handle the light source differently. Some designs can use external or remote laser modules, helping separate laser generation from the hottest part of the compute package.
But even with remote lasers, the PIC, EIC and associated optical structures must operate reliably beside high-power silicon.
This means that advanced packaging and liquid cooling are increasingly connected engineering problems.
As rack power density moves upward, cooling can no longer be considered only at the server level. Thermal design is moving toward the package itself — managing logic, HBM, electrical interfaces and potentially photonic components as one system.
Serviceability Remains an Open Question
Pluggable optics has one major operational advantage: replacement is simple.
If a pluggable transceiver fails, a technician can remove the module without replacing the processor or switch ASIC.
CPO changes that maintenance model.
Once expensive optical engines become part of the compute or switching package, failure isolation, replacement strategy and manufacturing yield become much more important.
The industry is already developing approaches such as detachable fiber interfaces and remote laser modules, but serviceability will remain an important consideration as CPO moves from demonstrations into large-scale data-center deployment.
Samsung Is Not Alone
CPO has moved well beyond a laboratory research topic.
TSMC is developing its COUPE — Compact Universal Photonic Engine — technology to integrate silicon photonics with electrical control chips. TSMC has said COUPE volume production is expected in 2026, while a CoWoS-based CPO platform for high-end network switches is also under development.
Broadcom has already demonstrated and delivered 51.2-Tbps CPO switch technology aimed directly at large-scale AI networks.
Intel has demonstrated an optical compute-interconnect chiplet co-packaged with a CPU and says the architecture is designed to extend to GPUs, IPUs and other processors.
Samsung’s strategy is especially noteworthy because it connects CPO with the company’s broader capabilities in foundry manufacturing, HBM, silicon integration and advanced packaging.
HBM Solves Memory Bandwidth. CPO Solves Communication Bandwidth.
The relationship between HBM and CPO may ultimately define the next generation of AI packages.
HBM addresses the problem of feeding data into the processor at extremely high speed.
CPO addresses the next problem: moving that data between processors and across the AI system without allowing interconnect power and electrical signal loss to become the dominant constraint.
The architecture can therefore be understood as two complementary movements:
Logic ↔ HBM: high-bandwidth memory communication
Logic ↔ CPO: high-bandwidth optical system communication
And both increasingly depend on a third infrastructure technology:
advanced thermal management.
The AI Package Is Becoming the System
The significance of Samsung’s CPO demonstration is therefore larger than the optical engine itself.
It illustrates how the boundaries between semiconductor manufacturing, packaging, memory, networking and cooling are beginning to disappear.
The next major AI platform may increasingly be defined by the integration of:
Advanced Logic + HBM + Optical I/O + Advanced Packaging + Liquid Cooling
In that environment, transistor scaling remains important, but it is no longer sufficient by itself.
The winners may be the companies that can integrate compute, memory and optics at high yield — and then keep the entire package electrically, optically and thermally stable at enormous data rates.
CPO is therefore not simply the next optical networking technology. It is becoming one of the central packaging technologies of the AI era.
Photo and field observation: Samsung CPO concept displayed at ASPS 2026, Suwon Convention Center, South Korea. DATAAD.