High Bandwidth Memory is entering a fundamental architectural transition.
Until HBM3E, competition was largely discussed in terms of DRAM process technology, stacking height, packaging yield and thermal management. With HBM4, however, another semiconductor has become just as important as the stacked DRAM itself: the logic Base Die located underneath the memory stack.
This Base Die is effectively becoming the gateway between the GPU and HBM.
Samsung: 4nm Logic Under the HBM Stack
Samsung Electronics' HBM4 combines its 1c-generation DRAM with a 4nm logic Base Die manufactured by Samsung Foundry. Samsung says its HBM4 supports a 2,048-I/O interface and bandwidth of up to approximately 3.3 TB/s per stack.
This represents a major change from previous HBM generations. The Base Die is no longer simply a passive layer that routes signals between stacked DRAM and the processor. It increasingly contains sophisticated logic responsible for high-speed interfaces, power management and communication with GPUs and AI accelerators.
Samsung has continued the same 4nm Base Die strategy for HBM4E, while increasing I/O performance to as much as 16 Gbps per pin and targeting bandwidth of up to approximately 4 TB/s per HBM stack.
SK hynix Takes a Different Foundry Route
SK hynix is pursuing a different manufacturing strategy.
The company has officially confirmed that beginning with HBM4 it is adopting TSMC advanced logic technology for the Base Die, replacing the internally produced Base Die architecture used through previous HBM generations.
Industry reports generally identify the HBM4 Base Die as being manufactured using a TSMC 12nm-class logic process. SK hynix itself, however, publicly describes it more broadly as a TSMC advanced logic process rather than specifying the exact node.
The contrast is significant:
Technology Samsung HBM4 SK hynix HBM4 DRAM Core Die 1c DRAM 1b DRAM Base Die Samsung Foundry logic TSMC logic Reported Base Die Process 4nm 12nm-class* Interface 2,048 I/O 2,048 I/O Strategic Model Memory + Foundry integration Memory + TSMC partnership
*SK hynix officially confirms the use of TSMC advanced logic for HBM4; the 12nm node is based on industry reporting.
The Most Important Part May Be the PHY
One of the most interesting changes inside the Base Die is the growing importance of the PHY, or Physical Layer interface.
The PHY is the high-speed electrical interface responsible for moving data between the HBM package and the GPU or AI accelerator. As AI processors consume increasingly larger amounts of data, improving the PHY affects not only theoretical bandwidth but also signal integrity, latency, power consumption and thermal behavior.
Samsung specifically identifies its D2D PHY, or Die-to-Die Physical Layer, as the high-speed communication block between HBM and GPUs.
Interestingly, this PHY is also becoming one of the major heat-generating areas inside the Base Die. Samsung is therefore developing dedicated thermal structures around the PHY for future HBM products.
HBM4E: The “E” Is About Enhancement
HBM4E should therefore not be understood simply as another stack of faster DRAM.
The “E” represents an enhanced generation of HBM4, combining higher I/O speed, greater bandwidth, improved power efficiency and increasingly optimized GPU-to-memory communication.
Samsung's HBM4E reaches up to 16 Gbps per pin, more than 20% above its HBM4 generation, while SK hynix has also announced 12-layer HBM4E samples capable of up to 16 Gbps per pin and more than 20% improved power efficiency.
SK hynix also says its latest interface and design optimization reduces data-transfer latency, directly connecting HBM development with AI training and inference efficiency.
From Standard Memory to Custom HBM
This transition has an even larger implication.
As more logic functions move into the Base Die, HBM can increasingly be designed specifically for an individual GPU, AI accelerator or ASIC.
Instead of every accelerator using essentially the same standardized memory, future HBM could contain logic and interfaces optimized for a specific NVIDIA, AMD, hyperscaler or custom AI processor architecture.
This is why both Samsung and SK hynix are already discussing Custom HBM.
The Base Die may eventually incorporate functions that previously belonged inside the GPU or accelerator itself. The boundary between “memory” and “processor” is beginning to blur.
Why This Matters for AI Infrastructure
The AI industry's problem is no longer simply how fast a GPU can calculate.
It is increasingly about how quickly enormous datasets can be delivered to thousands of GPU cores while consuming the least possible electrical power.
HBM4 doubles the interface width from the previous 1,024-bit generation to 2,048 bits. But beyond that number, the real technological battle is moving into the Base Die, PHY, advanced packaging and thermal architecture.
For AI data centers, this means future system performance may depend increasingly on four technologies working together:
GPU architecture → PHY/interface → HBM Base Die → stacked DRAM.
The memory can no longer be considered an independent component attached beside the GPU. It is becoming part of the AI computing architecture itself.
DATAAD View
The most important development visible in HBM4 is not simply “faster memory.”
It is the transformation of HBM from a memory product into a memory-and-logic system.
Samsung's 4nm Base Die strategy and SK hynix's collaboration with TSMC represent two different approaches to the same destination: placing more intelligence between the GPU and the DRAM stack.
As HBM4E and Custom HBM arrive, competition will increasingly be decided by who can design the most efficient communication path between compute and memory.
In the AI era, the distance between GPU and memory is becoming one of the most valuable pieces of semiconductor real estate.